This invention relates to semiconductor devices, and more particularly to sense amplifier circuits for dynamic read/write memory devices.
Dynamic MOS read/write memory devices have been constructed using bistable latches as differential sense amplifiers generaly as shown in U.S. Pat. No. 4,081,701 (a 16K dynamic RAM) issued to White, McAdams and Redwine, or U.S. Pat. No. 4,239,993 (a 64K dynamic RAM) issued to McAlexander, White and Rao, both assigned to Texas Instruments. These prior devices employed all N-channel transistors in the latches of the sense amplifiers. When memory devices of this type are manufactured in higher densities, such as 256K and 1-Megabit and beyond, the need for lower current per sense amplifier necessitates use of CMOS latches, and the problem of fast and reliable sensing, with circuits which may be manufactured at reasonable yields, becomes formidible.
In a dynamic RAM the sensing operation is critically dependent upon the latch transistors. These transistors must be balanced in threshold voltage Vt, and in KP, to within 10% for reliable operation. The prior sense amplifiers using only N-channel transistors required active pull-up circuits to produce a full rail-to-rail separation of the bit lines. CMOS latches provide rail-to-rail separation without such pull-up circuitry. However, the latch is less reliable when P-channel transistors are used in the initial sensing.
In a 1-Megabit DRAM that is refreshed at 512 per period, there are 2048 sense amplifiers which flip at the same time during an active cycle. Each one of these requires current to charge a bit line to Vdd, or discharge a bit line to Vss, or both, depending upon the precharge level. The voltage supply to the chip thus sees a large current spike in a short time period; as the access time is increased, the magnitude of the current spike increases. Thus, careful sizing of the latch and return transistors to minimize unnecessary current drain is advantageous.
It is the principal object of this invention to provide an improved sense amplifier circuit for high density dynamic RAM devices, particularly for high-speed, low power devices which may be economically manufactured. Another object is to provide a sense amplifier circuit for a CMOS dynamic RAM in which the size is minimized and reliability is improved. A further object is to provide high speed, low current circuitry for semiconductor devices which contain bistable or latch circuits and the like.